Wupper: PCIe DMA Engine for Xilinx FPGAs

Hardware

Clocking

The PCI Express end point core runs at 250 MHz, this clock is generated from a 100 MHz reference clock source from the connector fingers

!! clock stability is fundamental for PCI Express to work!!

Another user application clock needs to be provided for the register map synchronization stage

Qualified platforms

The example design has been created for the Virtex-7 FPGA VC709 Connectivity Kit, featuring a Xilinx XC7VX690T-2FFG1761C FPGA.
This FPGA is equipped with a PCI Express Gen3 hard block.

The design has been ported to:

• Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit, featuring a Xilinx XCKU040-2FFVA1156E FPGA,
• Hi-Tech Global HTG-710, featuring a Xilinx XC7VX690T-2FFG1761C FPGA
• BittWare XUPP3R-VU9P, featuring a xcvu9p-flgb2104-2-e FPGA and PCIe Gen4x8 (or dual x8 bifurcated) supported and working
• Xilinx VCU128, featuring a Xilinx XCVU37P-L2FSVH2892E FPGA and PCIe Gen4x8 (or dual x8 bifurcated) supported and working
• Xilinx VMK180, featuring a Xilinx XCVM1802-MSEVSVA2197 FGPA (ACAP) and PCIe Gen4x8 supported and working